As the geometries of semiconductor devices and particularly MOS transistors are being scaled to continually smaller dimensions, there is a desire for shorter gate lengths. However, as the transistor gate lengths continue to shrink the effects of p-poly sidewall depletion on PMOS transistor performance has become problematic.
It is believed that the problems are due, in part, to a larger portion of the polysilicon gate depletion being controlled by the edge depletion. This reduces the effective gate length of the device without reducing the physical gate length of the device, which in turn causes a higher concentration of a halo or pocket implant to be used. Unfortunately, as a higher concentration of the halo or pocket implant is used, the edge depletion region of the polysilicon gate electrode again increases, which further causes an even higher concentration of the halo or pocket implant to be used.
The increased edge depletion region is believed to be a function of the P-type dopant from the polysilicon gate electrode segregating from the sidewall of the polysilicon gate electrode, while the N-type dopant from the halo or pocket implant piling up at the sidewall of the polysilicon gate electrode. What results is an insufficient net P-type doping at the sidewalls of the polysilicon gate electrode, and thus a reduction in the effective gate length of the polysilicon gate electrode. This is not only a cyclical problem that feeds itself, but the carrier injection efficiency of the transistor is substantially degraded as a result of the increasingly higher halo or pocket implant concentrations.
The industry has addressed this problem using a number of different techniques. Most notably, the industry attempted to change from using P-type doped polysilicon gate electrodes to P-type doped silicon germanium gate electrodes. While the P-type doped silicon germanium gate electrodes substantially reduce the issues of the gate sidewall depletion, they are currently incompatible with NMOS devices. Accordingly, the industry would be forced to use polysilicon gate electrodes for the NMOS devices while using the silicon germanium gate electrodes for the PMOS devices, which is unreasonable.
Accordingly, what is needed in the art is a polysilicon gate electrode and method of manufacture therefor that does not experience the sidewall depletion issues experienced by the prior art devices.